This invention relates to semiconductor devices, and more specifically relates to such devices having a planar configuration, which are particularly suitable for use in high density integrated circuits, and also relates to a method of fabrication of such devices.
As the semiconductor devices in integrated circuits become smaller and more closely packed, the upper layers of the devices, such as the metal interconnect patterns, must accommodate more abrupt changes in surface topography caused by the smaller lateral dimensions of the devices. In some cases, deviations from planarity, sometimes called "steps", cannot be covered completely, so that discontinuities occur in the overlying metal layer. The problem is accentuated as more layers are added, such as in the case of interconnected multi-level integrated circuits, creating more complicated surface topographies having more and larger steps.
Etching techniques are known which will "planarize" a non-planar surface. For example, U.S. Pat. No. 4,025,411 describes a process in which the non-planar surface of a semiconductor device is made planar by first applying a layer of liquid photoresist over the uneven surface, then allowing the photoresist to solidify, and finally etching the surface by a physical etching method (for example, RF sputter etching or ion milling) which removes the photoresist and the underlying material at about the same rate. Other planarization techniques for use with solid state devices are described in U.S. Pat. Nos. 4,073,054; 4,455,193; and 4,470,874.
As device miniaturization approaches the sub-micron level, another problem is encountered, namely line width control, or LWC, that is, the ability to print and etch a line within the required dimensional tolerances. Thus, for example, it becomes difficult in the fabriction of MOS (metal oxide semiconductor) transistors to accurately control the dimensions of a gate electrode having a length of 1 micron or less. Such a gate is typically formed by first depositing a polysilicon layer over an insulating oxide layer, masking the polysilicon layer, and then etching away the unmasked portions of the polysilicon layer to leave a gate electrode of the desired configuration. The materials currently in use for etching polysilicon generally cannot provide the desired LWC due to a tendency both to attack the photoresist and to etch the polysilicon isotropically, resulting in undercutting of the mask.
Still another problem encountered in device miniaturization is mask alignment tolerance. For example, the masks employed in the formation of the polysilicon gate and the overlying contact can generally be aligned with an accuracy of only about + or -0.75 microns. A total misalignment of up to + or -1.50 microns is possible between two levels aligned to a third.
Accordingly, it is a principal object of the invention to provide an MOS device having a planar configuration which will be particularly suitable for use in high density integrated circuits.
It is another object of the invention to provide a fabrication technique for such a planar semiconductor device which has improved line width and alignment control, and which is therefor particularly suitable for the production of sub-micron semiconductor devices.